As the complexity of integrated circuits (ICs) increases and access to their internal circuit nodes becomes harder, properly testing such devices becomes a major bottleneck during their prototyping, development, production, and maintenance. As a result, designs with BIST implementation have become commonplace. In a BIST implementation, circuitry (which is intended solely to support testing) is included in an IC or in a system including ICs.
The current generation of products involves integrating high numbers of memory modules. With the increasing need for bandwidth, the trend is to also increase the memory size. The resulting technology, in response to the challenge of integrating memory modules with increased sizes, introduces new failure modes. Because it is currently hard to predefine the type of defects, which can appear in these memory arrays, the current state of the art involves implementing several algorithms on chip, such as March C, checkerboard, and address uniqueness. This approach, however, can only provide a temporary solution since as the technology progresses the BIST algorithms need to be redesigned to take new memory defects into consideration as well as new requirements such as the need to initialize a particular array. Accordingly, this approach can be very expensive (e.g., in terms of development) and is partially ineffective (especially for memory modules that have already been fabricated).